diff --git a/public/blog/thinkpad-t440p-coreboot-guide/eeprom_chip_4mb.webp b/public/blog/thinkpad-t440p-coreboot-guide/eeprom_chip_4mb.webp
new file mode 100644
index 0000000..7adc1ea
Binary files /dev/null and b/public/blog/thinkpad-t440p-coreboot-guide/eeprom_chip_4mb.webp differ
diff --git a/public/blog/thinkpad-t440p-coreboot-guide/eeprom_chip_8mb.webp b/public/blog/thinkpad-t440p-coreboot-guide/eeprom_chip_8mb.webp
new file mode 100644
index 0000000..7adc1ea
Binary files /dev/null and b/public/blog/thinkpad-t440p-coreboot-guide/eeprom_chip_8mb.webp differ
diff --git a/public/blog/thinkpad-t440p-coreboot-guide/spi_flasher_assembly.webp b/public/blog/thinkpad-t440p-coreboot-guide/spi_flasher_assembly.webp
new file mode 100644
index 0000000..aeca719
Binary files /dev/null and b/public/blog/thinkpad-t440p-coreboot-guide/spi_flasher_assembly.webp differ
diff --git a/public/scripts b/public/scripts
index 21af456..a665473 160000
--- a/public/scripts
+++ b/public/scripts
@@ -1 +1 @@
-Subproject commit 21af45674efb1d56010f8abdb629a1c3867551d6
+Subproject commit a6654739034d7be09043c19dbc51e360c1a15772
diff --git a/src/content/blog/thinkpad-t440p-coreboot-guide.mdx b/src/content/blog/thinkpad-t440p-coreboot-guide.mdx
index 25f6cc3..d820d03 100644
--- a/src/content/blog/thinkpad-t440p-coreboot-guide.mdx
+++ b/src/content/blog/thinkpad-t440p-coreboot-guide.mdx
@@ -44,14 +44,20 @@ Install the following programs. These will be needed to compile coreboot and fla
+`usbutils` provides `lsusb` (used to verify the CH341A). `chafa` and the
+`libwebp` tools are optional — the interactive script uses them to render
+reference images inline in your terminal when supported (and to transcode
+webp images to png if your chafa build doesn't support webp natively).
+Without them the script falls back to printing a URL.
+
## Disassembling the Laptop
1. **Power off your laptop**: Make sure your T440p is completely powered off and unplugged from any power source.
2. **Remove the battery**: Flip the laptop over and remove the battery by sliding the latch to the unlock position and lifting it out.
@@ -59,24 +65,39 @@ Install the following programs. These will be needed to compile coreboot and fla
## Locating the EEPROM Chips
-In order to flash the laptop, you will need to have access to two EEPROM chips located next to the sodimm RAM.
+In order to flash the laptop, you will need to have access to two EEPROM chips
+located next to the SODIMM RAM. They are different sizes and hold different
+firmware — read them in the order shown below.
-
+The **4MB (top)** chip — smaller, farther from the CPU:
+
+
+
+The **8MB (bottom)** chip — larger, closer to the CPU, holds the Intel ME firmware:
+
+
## Assembling the SPI Flasher
Place the SPI flasher ribbon cable into the correct slot and make sure its the 3.3v variant
-
+
-After the flasher is ready, connect it to your machine and ensure its ready to use:
+After the flasher is ready, plug it into a USB port on your machine (leave the clip
+unattached for now) and confirm the kernel sees it:
-
-Flashrom should report that programmer initialization was a success.
+A matching line (e.g. `Bus 001 Device 00X: ID 1a86:5512 QinHeng Electronics`)
+confirms the programmer is plugged in and the host recognises it.
+
+> Do **not** run `flashrom --programmer ch341a_spi` at this stage — with no
+> chip clipped on, flashrom will report "No EEPROM/flash device found" and
+> exit non-zero. That's expected, not a failure of the programmer. The chip
+> probe happens in the next section, paired with the actual read.
## Extracting Original BIOS
@@ -89,11 +110,14 @@ the T440p will be done.
client:load
/>
-Next, extract the original rom from both EEPROM chips. This is
-done by attaching the programmer to the correct chip and running
-the subsequent commands. It may take longer than expected, and
-ensuring the bios was properly extracted is important before proceeding
-further.
+Next, extract the original ROM from both EEPROM chips. Do the **4MB (top)
+chip first** — it's the smaller of the two, so reads finish faster and any
+setup issues (clip alignment, pin 1, voltage) surface quickly. Then move
+the clip to the **8MB (bottom) chip**.
+
+Each chip is read twice so the two reads can be diffed to catch flaky
+contact. The reads can take a while (tens of seconds to a couple of
+minutes per pass) — that's normal.